This invention relates to an electric circuit containing an integral phase-locked loop, and, more particularly, to an improvement thereof whereby the phase-locked loop may be selectively disabled to permit operation of the circuit in a mode in which the loop is not required.
2. Description of the Prior Art
Recently, the advantageous features of the phase-locked loop (hereinafter abbreviated to PLL) have been widely utilized, for instance, in the fields of FM detecting circuits, FM stereophonic multiplex circuits, and AM detecting circuits, and integrated circuits for these applications are readily available on the market. The PLL inherently comprises a phase difference detector, a d.c. amplifier, and a voltage-controlled oscillator which is continuously operated even in an operational mode of the circuit where the PLL is not utilized. The drawback of such an arrangement is that the output oscillation signal from the voltage-controlled oscillator, including higher harmonics, interferes, with other devices, such as audio circuits. In view of this drawback, it would be advantageous to put the PLL in an inoperative state in the cases where the PLL is utilized in a circuit wherein two series of amplifiers are employed, as in the cases of simply reproducing recorded discs or recorded tapes. Of course, it is possible to put the PLL into an inoperative state by merely turning the power source to an OFF state. However, ON-OFF operations of the power source cause transient phenomena in the circuit which in turn give rise to the creation of noise in the sound from the loudspeakers.